D.V. Efanov, V.V. Sapozhnikov, Vl.V. Sapozhnikov
Èlektron. model. 2018, 41(2):39-62
https://doi.org/10.15407/emodel.41.02.039
ABSTRACT
The authors analyzed the feature of detection ability in data vectors by modified weight-bits andThe authors analyzed the feature of detection ability in data vectors by modified weight-bits andweight-transition sum codes, which were constructed using a sequence of weights that form a naturalseries of numbers. The article presents the conditions for constructing a family of weightedcodes with the detection of any single error in data vectors of a given length m. The key characteristicsof weighted sum code are determined, which determine the conditions for their use in buildingreliable logic devices. A classification of weighted sum codes with weight coefficients from anatural series of numbers has been developed.
KEYWORDS
testable systems, sum code, Berger code, weighted codes with summation, codetestable systems, sum code, Berger code, weighted codes with summation, codeproperties, data vector, undetectable error.
REFERENCES
1. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Khristov, H.A. and Gavzov, D.V. (1995), Metody1. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Khristov, H.A. and Gavzov, D.V. (1995), Metodypostroeniya bezopasnykh mikroelektronnykh sistem zheleznodorozhnoy avtomatiki [Methodsfor constructing safety microelectronic systems for railway automation], Transport,Moscow, Russia.
2. Fujiwara, E. (2006), Code Design for Dependable Systems: Theory and Practical Applications,John Wiley & Sons, New Jersey, USA.
https://doi.org/10.1002/0471792748
3. Ubar, R., Raik, J. and Vierhaus, H.T. (2011), Design and Test Technology for DependableSystems-on-Chip, IGI Global, Hershey, New York, USA.
https://doi.org/10.4018/978-1-60960-212-3
4. Drozd, A.V., Kharchenko, V.S. and Antoshchuk, S.G. (2012), Rabochee diagnostirovaniebezopasnykh informatsionno-upravlyayuschikh sistem [Objects and Methods of On-LineTesting for Safe Instrumentation and Control Systems], National Aerospace University,Kharkov, Ukraine.
5. Berger, J.M. (1961), “A Note on Error Detection Codes for Asymmetric Channels”, Informationand Control, Vol. 4, no. 1, pp. 68-73. DOI:
https://doi.org/10.1016/S0019-9958(61)80037-5.
6. Busaba, F.Y. and Lala, P.K. (1994), “Self-Checking Combinational Circuit Design for Singleand Unidirectional Multibit Errors”, Journal of Electronic Testing: Theory and Applications,no. 1, pp. 19-28. DOI: https://doi.org/10.1007/BF00971960.
7. Matrosova, A.Yu., Levin, I. and Ostanin, S.A. (2000), “Self-Checking Synchronous FSMNetwork Design with Low Overhead”, VLSI Design, Vol. 11, no. 1, pp. 47-58. DOI:
https://doi.org/10.1155/2000/46578.
8. Ostanin, S. (2017), “Self-Checking Synchronous FSM Network Design for Path DelayFaults”, Proceedings of the 15th IEEE East-West Design & Test Symposium(EWDTS`2017), Novi Sad, Serbia, September 29-October 2, 2017, pp. 696-699. DOI:
https://doi.org/10.1109/EWDTS.2017.8110129.
9. Saposhnikov, V.V., Morosov, A., Saposhnikov, Vl.V. and Göessel, M. (1998), “A New DesignMethod for Self-Checking Unidirectional Combinational Circuits”, Journal of ElectronicTesting: Theory and Applications, Vol. 12, no. 1-2, pp. 41-53. DOI:
https://doi.org/10.1023/A:1008257118423.
10. Göessel, M., Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New Methods ofConcurrent Checking, Springer Science+Business Media, Nederland.
11. Nicolaidis, M. and Zorian, Y. (1998), “On-Line Testing for VLSI – A Compendium of Approaches”,Journal of Electronic Testing: Theory and Applications, no. 12, pp. 7-20. DOI:
https://doi.org/10.1023/A:1008244815697.
12. Mitra, S. and McCluskey, E.J. (2000), “Which Concurrent Error Detection Scheme toÑhoose?”, Proceeding of the International Test Conference, USA, Atlantic City, October03-05, 2000, pp. 985-994. DOI: https://doi.org/10.1109/TEST.2000.894311.
13. Sogomonyan, E.S. and Slabakov, E.V. (1989), Samoproveryaemye ustroystva i otkazoustoychivyesistemy [Self-checking devices and failover systems], Radio i svyaz, Moscow, USSR.
14. Piestrak, S.J. (1995), Design of Self-Testing Checkers for Unidirectional Error DetectingCodes, Wroclaw Polytechnic University, Wroclaw, Poland.
15. Ghosh, S., Basu, S. and Touba, N.A. (2005), “Synthesis of Low Power CED Circuits Basedon Parity Codes”, Proceeding of the 23rd IEEE VLSI Test Symposium (VTS’05), 2005, pp.315-320.
https://doi.org/10.1109/VTS.2005.80
16. Kubalík, P. and Kubatova, H. (2005), “Parity Codes Used for On-Line Testing in FPGA”,Acta Polytechnika, Vol. 45, no. 6, pp. 53-59.
17. Aksyonova, G.P. (2008), “On Functional Diagnosis of Discrete Devices Under Imperfect Data Processing Conditions”, Problemy upravleniya, no. 5, pp. 62-66.
18. Sapozhnikov, V., Sapozhnikov, Vl. and Efanov, D. (2015), “Modular Sum Code in BuildingTestable Discrete Systems”, Proceeding of the 13th IEEE East-West Design & Test Symposium(EWDTS`2015), Batumi, Georgia, September 26-29, 2015, pp. 181-187. DOI:
https://doi.org/10.1109/EWDTS.2015.7493133.
19. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2015), “Applications of ModularSummation Codes to Concurrent Error Detection Systems for Combinational BooleanCircuits”, Avtomatika i telemekhanika, no. 10, pp. 152-169.
https://doi.org/10.1134/S0005117915100112
20. Das, D. and Touba, N.A. (1999), “Synthesis of Circuits with Low-Cost Concurrent Error DetectionBased on Bose-Lin Codes”, Journal of Electronic Testing: Theory and Applications,Vol. 15, no. 1-2, pp. 145-155. DOI: https://doi.org/10.1023/A:1008344603814.
21. Cherepanova, M.R. (2016), “A study into influence of sum code module value on structureredundancy of concurrent error detection systems”, Izv. Peterburgskogo un-ta putey soobscheniya,no. 2, pp. 279-288.
https://doi.org/10.20295/1815-588X-2016-2-179-188
22. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2012), “Formationof the Berger Modified Code with Minimum Number of Undetectable Errors of DataBits”, Elektronnoe modelirovanie, Vol. 34, no. 6, pp. 17-29.
23. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Effective method ofmodifying code with on-bits summation”, Izv. vuzov. Priborostroenie, Vol. 60, no. 11, pp.1020-1032. DOI:
https://doi.org/10.17586/0021-3454-2017-60-11-1020-1032.
24. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2014), “OnCodes with Summation of Data Bits in Concurrent Error Detection Systems”, Avtomatika itelemekhanika, no. 8, pp. 131-145.
https://doi.org/10.1134/S0005117914080098
25. Berger, J.M. (1961), “A Note on Burst Detection Sum Codes”, Information and Control,Vol. 4, no. 2-3, pp. 297-299, DOI: 10.1016/S0019-9958(61)80024-7.26. Das, D. and Touba, N.A. (1999), “Weight-Based Codes and Their Application to ConcurrentError Detection of Multilevel Circuits”, Proceeding of the 17th IEEE VLSI Test Symposium,USA, CA, Dana Point, April 25-29, 1999, pp. 370-376.
https://doi.org/10.1016/S0019-9958(61)80024-7
27. Das, D., Touba, N.A., Seuring, M. and Gossel, M. (2000), “Low Cost Concurrent Error DetectionBased on Modulo Weight-Based Codes”, Proceeding of the IEEE 6th InternationalOn-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3-5, 2000, pp. 171-176. DOI:
https://doi.org/10.1109/OLT.2000.856633.
28. Saposhnikov, V. and Saposhnikov, Vl. (1999), “New Code for Fault Detection in Logic Circuits”,Proceeding of the 4th International Conference on Unconventional Electromechanicaland Electrical Systems, St. PÂ, Russia, June 21-24, 1999, pp. 693-696.
29. Mehov, V., Saposhnikov, V., Sapozhnikov, Vl. and Urganskov, D. (2007), “Concurrent ErrorDetection Based on New Code with Modulo Weighted Transitions between InformationBits”, Proceedings of the 7th IEEE East-West Design & Test Workshop (EWDTW`2007),Erevan, Armenia, September 25-30, 2007, pp. 21-26.
30. Mekhov, V.B., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2008), “Checking of CombinationalCircuits Basing on Modification Sum Codes”, Avtomatika i telemekhanika, no. 8,pp. 153-165.
https://doi.org/10.1134/S0005117908080134
31. Dmitriev, V.V. (2015), “On the two weighing methods and their influence on properties ofsum codes of weighted transitions in functional logical scheme control systems”, Izv.Peterburgskogo un-ta putey soobscheniya, no. 3, pp. 119-129.
32. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V. and Kotenko, A.G. (2017), “ModuloCodes with Summation of Weighted Transitions with Natural Number Sequence of Weights”,Trudy SPIIRAN, no. 1, pp. 137-164. DOI:
https://doi.org/10.15622/sp.50.6.
33. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Modulo weighted codeswith summation with minimum number of undetectable errors in data vectors”, Elektron.modelirovanie, Vol. 39, no. 4, pp. 69-88.
https://doi.org/10.15407/emodel.39.04.069
34. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Codes with Summation34. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Codes with Summationwith a Sequence of Weight Coefficients, Forming a Natural Series of Numbers, in ConcurrentError Detection Systems”, Elektron. modelirovanie, Vol. 39, no. 5, pp. 37-58.
https://doi.org/10.15407/emodel.39.05.037
35. Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2017), “The Synthesis of Self-CheckingCombinational Devices Based on Properties of Codes With Summation of Weighted Transitionsand Selection of Testable Outputs Groups”, Proceeding of the 15th IEEE East-WestDesign & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29-October 2,2017, pp. 671-677. DOI:
https://doi.org/10.1109/EWDTS.2017.8110075.
36. Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2017), “Modified codes with weightedtransitionssummation in concurrent error detection systems of combinational circuits”,Trudy In-ta sistemnogo programmirovaniya RAN, Vol. 29, no. 5, pp. 39-60. DOI:
https://doi.org/10.15514/ISPRAS-2017-29(5)-3.
2. Fujiwara, E. (2006), Code Design for Dependable Systems: Theory and Practical Applications,John Wiley & Sons, New Jersey, USA.
https://doi.org/10.1002/0471792748
3. Ubar, R., Raik, J. and Vierhaus, H.T. (2011), Design and Test Technology for DependableSystems-on-Chip, IGI Global, Hershey, New York, USA.
https://doi.org/10.4018/978-1-60960-212-3
4. Drozd, A.V., Kharchenko, V.S. and Antoshchuk, S.G. (2012), Rabochee diagnostirovaniebezopasnykh informatsionno-upravlyayuschikh sistem [Objects and Methods of On-LineTesting for Safe Instrumentation and Control Systems], National Aerospace University,Kharkov, Ukraine.
5. Berger, J.M. (1961), “A Note on Error Detection Codes for Asymmetric Channels”, Informationand Control, Vol. 4, no. 1, pp. 68-73. DOI:
https://doi.org/10.1016/S0019-9958(61)80037-5.
6. Busaba, F.Y. and Lala, P.K. (1994), “Self-Checking Combinational Circuit Design for Singleand Unidirectional Multibit Errors”, Journal of Electronic Testing: Theory and Applications,no. 1, pp. 19-28. DOI: https://doi.org/10.1007/BF00971960.
7. Matrosova, A.Yu., Levin, I. and Ostanin, S.A. (2000), “Self-Checking Synchronous FSMNetwork Design with Low Overhead”, VLSI Design, Vol. 11, no. 1, pp. 47-58. DOI:
https://doi.org/10.1155/2000/46578.
8. Ostanin, S. (2017), “Self-Checking Synchronous FSM Network Design for Path DelayFaults”, Proceedings of the 15th IEEE East-West Design & Test Symposium(EWDTS`2017), Novi Sad, Serbia, September 29-October 2, 2017, pp. 696-699. DOI:
https://doi.org/10.1109/EWDTS.2017.8110129.
9. Saposhnikov, V.V., Morosov, A., Saposhnikov, Vl.V. and Göessel, M. (1998), “A New DesignMethod for Self-Checking Unidirectional Combinational Circuits”, Journal of ElectronicTesting: Theory and Applications, Vol. 12, no. 1-2, pp. 41-53. DOI:
https://doi.org/10.1023/A:1008257118423.
10. Göessel, M., Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New Methods ofConcurrent Checking, Springer Science+Business Media, Nederland.
11. Nicolaidis, M. and Zorian, Y. (1998), “On-Line Testing for VLSI – A Compendium of Approaches”,Journal of Electronic Testing: Theory and Applications, no. 12, pp. 7-20. DOI:
https://doi.org/10.1023/A:1008244815697.
12. Mitra, S. and McCluskey, E.J. (2000), “Which Concurrent Error Detection Scheme toÑhoose?”, Proceeding of the International Test Conference, USA, Atlantic City, October03-05, 2000, pp. 985-994. DOI: https://doi.org/10.1109/TEST.2000.894311.
13. Sogomonyan, E.S. and Slabakov, E.V. (1989), Samoproveryaemye ustroystva i otkazoustoychivyesistemy [Self-checking devices and failover systems], Radio i svyaz, Moscow, USSR.
14. Piestrak, S.J. (1995), Design of Self-Testing Checkers for Unidirectional Error DetectingCodes, Wroclaw Polytechnic University, Wroclaw, Poland.
15. Ghosh, S., Basu, S. and Touba, N.A. (2005), “Synthesis of Low Power CED Circuits Basedon Parity Codes”, Proceeding of the 23rd IEEE VLSI Test Symposium (VTS’05), 2005, pp.315-320.
https://doi.org/10.1109/VTS.2005.80
16. Kubalík, P. and Kubatova, H. (2005), “Parity Codes Used for On-Line Testing in FPGA”,Acta Polytechnika, Vol. 45, no. 6, pp. 53-59.
17. Aksyonova, G.P. (2008), “On Functional Diagnosis of Discrete Devices Under Imperfect Data Processing Conditions”, Problemy upravleniya, no. 5, pp. 62-66.
18. Sapozhnikov, V., Sapozhnikov, Vl. and Efanov, D. (2015), “Modular Sum Code in BuildingTestable Discrete Systems”, Proceeding of the 13th IEEE East-West Design & Test Symposium(EWDTS`2015), Batumi, Georgia, September 26-29, 2015, pp. 181-187. DOI:
https://doi.org/10.1109/EWDTS.2015.7493133.
19. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2015), “Applications of ModularSummation Codes to Concurrent Error Detection Systems for Combinational BooleanCircuits”, Avtomatika i telemekhanika, no. 10, pp. 152-169.
https://doi.org/10.1134/S0005117915100112
20. Das, D. and Touba, N.A. (1999), “Synthesis of Circuits with Low-Cost Concurrent Error DetectionBased on Bose-Lin Codes”, Journal of Electronic Testing: Theory and Applications,Vol. 15, no. 1-2, pp. 145-155. DOI: https://doi.org/10.1023/A:1008344603814.
21. Cherepanova, M.R. (2016), “A study into influence of sum code module value on structureredundancy of concurrent error detection systems”, Izv. Peterburgskogo un-ta putey soobscheniya,no. 2, pp. 279-288.
https://doi.org/10.20295/1815-588X-2016-2-179-188
22. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2012), “Formationof the Berger Modified Code with Minimum Number of Undetectable Errors of DataBits”, Elektronnoe modelirovanie, Vol. 34, no. 6, pp. 17-29.
23. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Effective method ofmodifying code with on-bits summation”, Izv. vuzov. Priborostroenie, Vol. 60, no. 11, pp.1020-1032. DOI:
https://doi.org/10.17586/0021-3454-2017-60-11-1020-1032.
24. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2014), “OnCodes with Summation of Data Bits in Concurrent Error Detection Systems”, Avtomatika itelemekhanika, no. 8, pp. 131-145.
https://doi.org/10.1134/S0005117914080098
25. Berger, J.M. (1961), “A Note on Burst Detection Sum Codes”, Information and Control,Vol. 4, no. 2-3, pp. 297-299, DOI: 10.1016/S0019-9958(61)80024-7.26. Das, D. and Touba, N.A. (1999), “Weight-Based Codes and Their Application to ConcurrentError Detection of Multilevel Circuits”, Proceeding of the 17th IEEE VLSI Test Symposium,USA, CA, Dana Point, April 25-29, 1999, pp. 370-376.
https://doi.org/10.1016/S0019-9958(61)80024-7
27. Das, D., Touba, N.A., Seuring, M. and Gossel, M. (2000), “Low Cost Concurrent Error DetectionBased on Modulo Weight-Based Codes”, Proceeding of the IEEE 6th InternationalOn-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3-5, 2000, pp. 171-176. DOI:
https://doi.org/10.1109/OLT.2000.856633.
28. Saposhnikov, V. and Saposhnikov, Vl. (1999), “New Code for Fault Detection in Logic Circuits”,Proceeding of the 4th International Conference on Unconventional Electromechanicaland Electrical Systems, St. PÂ, Russia, June 21-24, 1999, pp. 693-696.
29. Mehov, V., Saposhnikov, V., Sapozhnikov, Vl. and Urganskov, D. (2007), “Concurrent ErrorDetection Based on New Code with Modulo Weighted Transitions between InformationBits”, Proceedings of the 7th IEEE East-West Design & Test Workshop (EWDTW`2007),Erevan, Armenia, September 25-30, 2007, pp. 21-26.
30. Mekhov, V.B., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2008), “Checking of CombinationalCircuits Basing on Modification Sum Codes”, Avtomatika i telemekhanika, no. 8,pp. 153-165.
https://doi.org/10.1134/S0005117908080134
31. Dmitriev, V.V. (2015), “On the two weighing methods and their influence on properties ofsum codes of weighted transitions in functional logical scheme control systems”, Izv.Peterburgskogo un-ta putey soobscheniya, no. 3, pp. 119-129.
32. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V. and Kotenko, A.G. (2017), “ModuloCodes with Summation of Weighted Transitions with Natural Number Sequence of Weights”,Trudy SPIIRAN, no. 1, pp. 137-164. DOI:
https://doi.org/10.15622/sp.50.6.
33. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Modulo weighted codeswith summation with minimum number of undetectable errors in data vectors”, Elektron.modelirovanie, Vol. 39, no. 4, pp. 69-88.
https://doi.org/10.15407/emodel.39.04.069
34. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Codes with Summation34. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Codes with Summationwith a Sequence of Weight Coefficients, Forming a Natural Series of Numbers, in ConcurrentError Detection Systems”, Elektron. modelirovanie, Vol. 39, no. 5, pp. 37-58.
https://doi.org/10.15407/emodel.39.05.037
35. Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2017), “The Synthesis of Self-CheckingCombinational Devices Based on Properties of Codes With Summation of Weighted Transitionsand Selection of Testable Outputs Groups”, Proceeding of the 15th IEEE East-WestDesign & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29-October 2,2017, pp. 671-677. DOI:
https://doi.org/10.1109/EWDTS.2017.8110075.
36. Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2017), “Modified codes with weightedtransitionssummation in concurrent error detection systems of combinational circuits”,Trudy In-ta sistemnogo programmirovaniya RAN, Vol. 29, no. 5, pp. 39-60. DOI:
https://doi.org/10.15514/ISPRAS-2017-29(5)-3.