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  5. VOL 45, NO 2 (2023)
  6. pp. 16-33

Vector–Logic Synthesis of Deductive Matrices for Fault Simulation

W. Gharibi 1, PhD, Prof., A. Hahanova 2, Cand. T. Sc, Ass. Prof., V. Hahanov 2,
D. Sc., Prof., S. Chumachenko 2, D. Sc., Prof., E. Litvinova 2, D. Sc., Prof., I. Hahanov 2

1 The University of Missouri-Kansas City MO 64110 USA,
  This email address is being protected from spambots. You need JavaScript enabled to view it.

2 Kharkiv National University of Radio Electronics,
  Ukraine, 61166, Kharkiv, Nauka Avenue, 14,
  (057) 7021 326, This email address is being protected from spambots. You need JavaScript enabled to view it.

Èlektron. model. 2023, 45(2):16-33

https://doi.org/10.15407/emodel.45.02.016

ABSTRACT

The main idea is to create vector-logic computing that uses only read-write transactions on address memory to process large data. The main task is to implement new simple and reliable models and methods of vector computing based on primitive read-write transactions in the technology of vector flexible interpretive simulation of digital system faults. Vector-logic computing is a computational process based on read-write transactions over bits of a binary vector of functionality, where the input data is the addresses of the bits. A vector method for the synthesis of deductive matrices for transporting input fault lists is proposed, which has a quadratic computational complexity. The method is a development of the deductive vector synthesis algorithm based on the truth table. The deductive matrix is intended for the synthesis and verification of tests using parallel simulation of faults, as addresses, based on a read-write transaction of deductive vector cells in memory.

KEYWORDS

vector computing, vector form of logic, matrix of deductive vectors, vector method for synthesizing a deductive matrix, read-write transaction, vector model of defects, functions and structures, deductive parallel fault simulation.

REFERENCES

  1. Gharibi V., Khakhanova A.V., Hahanov V.I., Chumachenko S.V., Litvinova E.I., Hahanov I.V. (2023), Vector-deductive Memory-based Transactions for Fault-as-address Si­mulation. Electronic modeling, no. 1, pp. 12-23.
    https://doi.org/10.15407/emodel.45.01.003
  2. Shannon C.E. (1958, 1993), Von Neumann's Contributions to Automata Theory Bulletin American Mathematical  Society,   64, Claude E. Shannon: Collected Papers. IEEE, pp. 831-835.
    https://doi.org/10.1090/S0002-9904-1958-10214-1
  3. Davis M. (1989), Emil Post's contributions to computer science. Fourth Annual Symposium on Logic in Computer Science, pp. 134-136.
    https://doi.org/10.1109/LICS.1989.39167
  4. What’s New in the 2022 Gartner Hype Cycle for Emerging Technologies, Accessed: https://www.gartner.com/en/articles/what-s-new-in-the-2022-gartner-hype-cycle-for-emerging-technologies, 02/08/2023.
  5. Wang P. et al. (2018), RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases. 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), Vienna, Austria, pp. 518-530.
    https://doi.org/10.1109/HPCA.2018.00051
  6. Takahashi N., Ishiura N. and Yajima S. (1994), Fault simulation for multiple faults by Boolean function manipulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. April, vol. 13, no. 4, pp. 531-535.
    https://doi.org/10.1109/43.275363
  7. Srivastava M., Goyal S.K., Saraswat A. and Gangil G. (2020), Simulation Models for Different Power System Faults. 2020 IEEE International Conference on Advances and Developments in Electrical and Electronics Engineering (ICADEE), pp. 1-6. 
    https://doi.org/10.1109/ICADEE51157.2020.9368915
  8. Menon and Chappell. Deductive Fault Simulation with Functional Blocks. IEEE Transactions on Computers. 1978, vol. C-27, no. 8, pp. 689-695. 
    https://doi.org/10.1109/TC.1978.1675175
  9. Pomeranz I. and Reddy S.M. (2001), Forward-looking fault simulation for improved static compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Oct. 2001, vol. 20. no. 10, pp. 1262-1265. 
    https://doi.org/10.1109/43.952743
  10. Navabi Z. (2011), Digital System Test and Testable Design. Using HDL Models and Architectures. Springer.
    https://doi.org/10.1007/978-1-4419-7548-5
  11. Hahanov V., Chumachenko S., Iemelianov I., Hahanov V., Larchenko L. and Daniyil T. (2017), Deductive qubit fault simulation. 2017 14th International Conference: The Expe­rience of Designing  and Application of  CAD Systems in Microelectronics (CADSM), pp. 256- 
    https://doi.org/10.1109/CADSM.2017.7916129
  12. Hahanov V., Gharibi W., Litvinova E. and Chumachenko S. (2019), Qubit-driven Fault Simulation. 2019 IEEE Latin American Test Symposium (LATS), pp. 1-7.
    https://doi.org/10.1109/LATW.2019.8704583
  13. Gharibi W., Devadze D., Hahanov V., Litvinova E. and Hahanov I. (2019), Qubit Test Synthesis Processor for SoC Logic. 2019 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, pp. 1-5. 
    https://doi.org/10.1109/EWDTS.2019.8884476
  14. Hahanov V. et al. (2021), Vector-Qubit models for SoC Logic-Structure Testing and Fault Simulation. 2021 IEEE 16th International Conference on the Experience of Designing and Application of CAD Systems (CADSM), pp. 24-28. 
    https://doi.org/10.1109/CADSM52681.2021
  15. Hahanov V.I., Hyduke S.M., Gharibi W., Litvinova E.I., Chumachenko S.V. and HahanovaV. (2014), Quantum Models and Method for Analysis and Testing Computing Systems. 2014 11th International Conference on Information Technology: New Generations, Las Vegas, NV, pp. 430-434. 
    https://doi.org/10.1109/ITNG.2014.125
  16. Karavay M., Hahanov V., Litvinova E., Khakhanova H. and Hahanova I. (2019), Qubit Fault Detection in SoC Logic. 2019 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, pp. 1-7. 
    https://doi.org/10.1109/EWDTS.2019.8884475
  17. Hahanov V., Gharibi W., Litvinova E. and Chumachenko S. (2019), Qubit-driven Fault Simulation. 2019 IEEE Latin American Test Symposium (LATS), Santiago, Chile, pp. 1-7. 
    https://doi.org/10.1109/LATW.2019.8704583
  18. Karavay M., Hahanov V., Litvinova E., Khakhanova H. and Hahanova I. (2019), Qubit Fault Detection in SoC Logic. 2019 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, pp. 1-7. 
    https://doi.org/10.1109/EWDTS.2019.8884475
  19. Hahanov V. Cyber Physical Computing for IoT-driven Services. New York: Springer. 2018. 
    https://doi.org/10.1007/978-3-319-54825-8
  20. Reinsalu U., Raik J., Ubar R. and Ellervee P. (2011), Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver, BC, pp. 164-170. 
    https://doi.org/10.1109/DFT.2011.42
  21. Pomeranz I. and Reddy S.M. (1998), A synthesis procedure for flexible logic functions. Proceedings Design, Automation and Test in Europe. Pp. 973-974. Doi: 10.1109/DATE. 1998.655995.
  22. D.B. (1972), A Deductive Method for Simulating Faults in Logic Circuits. IEEE Transactions on Computers. May 1972. Vol. C-21, No. 5, pp. 464-471. 
    https://doi.org/10.1109/T-C.1972.223542
  23. Vinod N. et al. (2020), Performance Evaluation of LUTs in FPGA in Different Circuit Topologies. 2020 International Conference on Communication and Signal Processing (ICCSP), pp. 1511-1515. 
    https://doi.org/10.1109/ICCSP48568.2020.9182074
  24. Efanov D. Pogodina T. (2023), Properties Investigation of Self-Dual Combinational Devi­ces with Calculation Control Based on Hamming Codes. Informatics and Automation. Vol. 22, Iss. 2, pp. 349-392.
    https://doi.org/10.15622/ia.22.2.5

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