V.V. Sapozhnikov, Dr Sc. (Eng.), Vl.V. Sapozhnikov, Dr Sc. (Eng.), D.V. Efanov, Cand. Sc. (Eng.),
Emperor Alexande I St.Petersburg State Transport University, 9 Moskovsky Ave, Saint Petersburg, 190031, Russian Federation, e-mail:
Èlektron. model. 2018, 40(3):41-62
https://doi.org/10.15407/emodel.40.03.041
ABSTRACT
The problem has been considered of constructing a class of codes with summation with the smallest total number of undetectable errors in data vectors for a given numbers of data and check bits. An algorithm is proposed for constructing modified modular codes with summation of weighted data bits with a sequence of weight coefficients that forms a natural series of numbers. Properties of a new class of codes are analyzed in comparison with known modular codes with summation of single indicators of digits. A classification and a detailed comparative analysis of modular codes with summation possessing the property of identifying any errors with odd multiplicities are given. The advantages and disadvantages of the new modified modular weighted codes with summation are shown.
KEYWORDS
technical diagnostics of discrete systems, summation code, Berger’s code, modular summation code, undetectable error, weighted summation codes, modified weighted summation code
REFERENCES
1. Aksjonova, G.P. (2008), “On functional diagnosis of discrete devices under imperfect data processing conditions, Problemy upravleniya, no. 5, pp. 62-66.
2. Ubar, R., Raik, J. and Vierhaus, H.-T. (2011), “Design and test technology for dependable systems-on-chip (Premier Reference Source)”, Information Science Reference, IGI Global, Hershey – New York, USA.
3. Mosin, S. (2012), “Methodology to design-for-testability automation for mixed-signal integrated circuits organization”, Proceedings of the 10th IEEE East-West Design & Test Symposium (EWDTS`2012), Kharkov, Ukraine, September 14-17, 2012, pp. 178-183.
4. Drozd, A., Drozd, J., Antoshchuk, S., et al. (2016), “Objects and methods of on-line testing: Main requirements and perspectives of development”, Proceedings of the 14th IEEE East-West Design & Test Symposium (EWDTS`2016), Yerevan, Armenia, October 14-17, 2016, pp. 72-76.
https://doi.org/10.1109/EWDTS.2016.7807750
5. Hahanov, V., Litvinova, E., Gharibi, W., et al. (2017), “Quantum memory-driven computing for test synthesis”, Proceedings of the 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29-October 2, 2017, pp. 63-68. DOI: 10.1109/EWDTS.2017.8110147.
https://doi.org/10.1109/EWDTS.2017.8110147
6. Tshagharyan, G., Harutyunyan, G., Shoukourian, S. and Zorian, Y. (2017), “Experimental study on Hamming and Hsiao codes in the context of embedded applications”, Ibid, Novi Sad, Serbia, September 29-October 2, 2017, pp. 25-28. DOI: 10.1109/EWDTS.2017.8110065.
https://doi.org/10.1109/EWDTS.2017.8110065
7. Borecky J., Kohlik M., Kubatova, H. (2017), “Parity driven reconfigurable duplex system”, Microprocessors and Microsystems, Vol. 52, pp. 251-260, DOI: 10.1016/j.micpro.2017. 06.015.
8. Piestrak, S.J. (1995), Design of self-testing checkers for unidirectional error detecting codes, Oficyna Wydawnicza Politechniki Wroclavskiej, Wroclaw, Poland.
9. Zeng, C. and McCluskey, E.J. (1999), “Finite state machine synthesis with concurrent error detection”, Proceedings of International Test Conference, Atlantic City, NJ, 1999, pp. 672-679, DOI: 10.1109/TEST.1999.805795.
https://doi.org/10.1109/TEST.1999.805795
10. Jha, N.K. and Gupta, S. (2003), Testing of digital systems, Cambridge University Press, Cambridge, UK.
https://doi.org/10.1017/CBO9780511816321
11. Fujiwara, E. (2006), Code design for dependable systems: Theory and practical applications, John Wiley & Sons, New Jersey, USA.
https://doi.org/10.1002/0471792748
12. Göessel, M., Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New methods of concurrent checking: Edition 1, Springer Science+Business Media B.V., Dodrecht, Netherlands.
13. Dinesh Babu, N. and Ramani, G. (2014), “Checkbit prediction for logic functions by using Dong’s code method”, Intern. Journal of Science and Research (IJSR), Vol. 3, Iss. 11, pp. 946-949.
14. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2015), “Errors classification in information vectors of systematic codes”, Izvestiya Vysshikh Uchebnykh Zavedeniy. Priborostroenie, Vol. 58, no. 5, pp. 333-343. DOI 10.17586/0021-3454-2015-58-5-333-343.
https://doi.org/10.17586/0021-3454-2015-58-5-333-343
15. Berger, J.M. (1961), “A note on error detecting codes for asymmetric channels”, Information and Control, Vol. 4, Iss. 1, pp. 68-73. DOI: 10.1016/S0019-9958(61)80037-5.
https://doi.org/10.1016/S0019-9958(61)80037-5
16. Sogomonyan, E.S. and Slabakov, E.V. (1989), Samoproveryaemye ustroystva i otkazoustoychivye sistemy [Self-checking devices and failover systems], Radio & Svyaz, Moscow, USSR.
17. Touba, N.A. and McCluskey, E.J. (1997), “Logic synthesis of multilevel circuits with concurrent error detection”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and System. Vol. 16, July, 1997, pp. 783-789.
https://doi.org/10.1109/43.644041
18. Nicolaidis, M. and Zorian, Y. (1998), “On-line testing for VLSI — a compendium of approaches”, Journal of Electronic Testing: Theory and Applications, no. 12, pp. 7-20. DOI:10.1023/A:1008244815697.
https://doi.org/10.1023/A:1008244815697
19. Mitra, S. and McCluskey, E.J. (2000), “Which concurrent error detection scheme to choose?”, Proceedings of International Test Conference, USA, Atlantic City, NJ, October 03-05, 2000, pp. 985-994. DOI: 10.1109/TEST.2000.894311.
https://doi.org/10.1109/TEST.2000.894311
20. Ostanin, S. (2017), “Self-checking synchronous FSM network design for path delay faults”, Proceedings of the 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29-October 2, 2017, pp. 696-699. DOI: 10.1109/EWDTS.2017.8110129.
https://doi.org/10.1109/EWDTS.2017.8110129
21. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2010), “On sum code properties in concurrent error detection systems”, Avtomatika i telemekhanika, no. 6, pp. 155-162.
22. Das, D., and Touba, N.A. (1999), “Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes”, Journal of Electronic Testing: Theory and Applications, Vol. 15, Issue 1-2, pp. 145-155. DOI: 10.1023/A:1008344603814.
https://doi.org/10.1023/A:1008344603814
23. Das, D. and Touba, N.A. (1999), “Weight-based codes and their application to concurrent error detection of multilevel circuits”, Proceedings of the 17th IEEE VLSI Test Symposium, USA, CA, Dana Point, April 25-29, 1999, pp. 370-376.
https://doi.org/10.1109/VTEST.1999.766691
24. Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2016), “Generic two-modulus sum codes for technical diagnostics of discrete systems problems”, Proceedings of the 14th IEEE East-West Design & Test Symposium (EWDTS`2016), Yerevan, Armenia, October 14-17, 2016, pp. 256-260. DOI: 10.1109/EWDTS.2016.7807713.
https://doi.org/10.1109/EWDTS.2016.7807713
25. Bose, B. and Lin, D.J. (1985), “Systematic unidirectional error-detection codes”, IEEE Transaction on Computers, Vol. C-34, Nov., pp. 1026-1032.
https://doi.org/10.1109/TC.1985.1676535
26. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2015), “Applications of modular summation codes to concurrent error detection systems for combinational Boolean circuits”, Avtomatika i telemekhanika, no. 10, pp. 152-169.
https://doi.org/10.1134/S0005117915100112
27. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V. and Cherepanova, M.R. (2016), “Modulo codes with summation in concurrent error detection systems. I. Ability of modulo codes to detect error in data vectors”, Elektronnoe modelirovanie, Vol. 38, no. 2, pp. 27-48.
28. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2012), “Formation of the Berger modified code with minimum number of undetectable errors of data bits”, Elektronnoe modelirovanie, Vol. 34, no. 6, pp. 17-29.
29. Blyudov, A.A., Efanov, D.V. Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2014), “On codes with summation of data bits in concurrent error detection systems”, Avtomatika i telemekhanika, no. 8, pp. 131-145.
https://doi.org/10.1134/S0005117914080098
30. Efanov, D., Sapozhnikov, V., Sapozhnikov, Vl. and Nikitin, D. (2015), “Sum code formation with minimum total number of undetectable errors in data vectors”, Proceedings of the 13th IEEE East-West Design &Test Symposium (EWDTS`2015), Batumi, Georgia, September 26-29, 2015, pp. 141-148. DOI: 10.1109/EWDTS.2015.7493112.
https://doi.org/10.1109/EWDTS.2015.7493112
31. Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2016), “On one method of formation of optimum sum code for technical diagnostics systems”, Proceedings of the 14th IEEE East-West Design & Test Symposium (EWDTS`2016), Yerevan, Armenia, October 14-17, 2016, pp. 158-163. DOI: 10.1109/EWDTS.2016.7807633.
https://doi.org/10.1109/EWDTS.2016.7807633
32. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2017), “Codes with summation with a sequence of weight coefficients, forming a natural series of numbers, in concurrent error detection systems”, Elektronnoe modelirovanie, Vol. 39, no. 5, pp. 37-58.
33. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V. and Kotenko, A.G. (2017), “Modulo codes with summation of weighted transitions with natural number sequence of weights”, Trudy SPIIRAN, no. 1, pp. 137-164. DOI: 10.15622/SP.50.6.
https://doi.org/10.15622/sp.50.6