2. Home
  3. ARCHIVE
  4. 2023
  5. VOL 45, NO 1 (2023)
  6. pp. 03-26

Vector-deductive Memory-based Transactions for Fault-as-address Simulation

W. Gharibi 1, PhD, Prof., A. Hahanova 2, Cand. T. Sc, Ass. Prof.,
V. Hahanov 2, D.Sc., Prof., S. Chumachenko 2, D.Sc., Prof.,
E. Litvinova 2, D.Sc., Prof., I. Hahanov 2

1 The University of Missouri-Kansas City, MO 64110 USA,
  This email address is being protected from spambots. You need JavaScript enabled to view it.
2 Kharkiv National University of Radio Electronics,
  Ukraine, 61166, Kharkiv, Nauka Avenue, 14,
  (057) 7021 326, This email address is being protected from spambots. You need JavaScript enabled to view it.

Èlektron. model. 2023, 45(1):03-26

https://doi.org/10.15407/emodel.45.01.003

ABSTRACT

The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. In the work, the transition to vector logic in the organization of computing and the elimination of traditional logic presented in the form of tables and analytical expressions were carried out. The use of read-write transactions on memory in the absence of a command system focuses the new vector-logic computing towards deterministic quantum architectures based on stable subatomic memory particles.

KEYWORDS

vector computing, vector form of logic, matrix of deductive vectors, table of synthesis of deductive vectors, analytical form of structures, deductive-vector method of fault analysis, digital circuit, vector model of defects, functions and structures, sequencer of vector deductive fault simulation.

REFERENCES

  1. Abramovici M., Breuer M.A. and Friedman A.D. (1998), Digital System Testing and Tes-table Design, Sc. Press.
  2. Takahashi N., Ishiura N. and Yajima S. (1994), "Fault simulation for multiple faults by Boolean function manipulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 4, pp. 531-535.
    https://doi.org/10.1109/43.275363
  3. Dobai R., Gramatova E. (2009), "Deductive Fault Simulation for Asynchronous Sequential Circuits," 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, pp. 459-464
    https://doi.org/10.1109/DSD.2009.129
  4. Chang H.Y., Chappell S.G, Elmendorf C.H., and Schmidt L.D. (1974), "Comparison of Parallel and Deductive Fault Simulation Methods," IEEE Transactions on Computers, C-23, no. 11, pp. 1132-1138, Nov. 1974.
    https://doi.org/10.1109/T-C.1974.223820
  5. Pomeranz I. and Reddy S.M., "Forward-looking fault simulation for improved static compaction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 10, pp. 1262-1265, Oct. 2001.
    https://doi.org/10.1109/43.952743
  6. Navabi Z. (2011). Digital System Test and Testable Design. Using HDL Models and Architectures. Springer.
    https://doi.org/10.1007/978-1-4419-7548-5
  7. Hahanova A.V. (2022), "Developing method of vector synthesis deductive logic for computer systems fault analysis," Herald of Advanced Information Technology, vol. 5, no. 2, pp. 102-112
    https://doi.org/10.15276/hait.05.2022.8
  8. Hahanov V., Gharibi W., Litvinova E. and Chumachenko S. (2019), "Qubit-driven Fault Simulation," 2019 IEEE Latin American Test Symposium (LATS), pp. 1-7.
    https://doi.org/10.1109/LATW.2019.8704583
  9. Gharibi W., Devadze D., Hahanov V., Litvinova E. and Hahanov I., (2019), "Qubit Test Synthesis Processor for SoC Logic," 2019 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, pp. 1-5.
    https://doi.org/10.1109/EWDTS.2019.8884476
  10. Hahanov V. et al., (2021), "Vector-Qubit models for SoC Logic-Structure Testing and Fault Simulation," 2021 IEEE 16th International Conference on the Experience of Designing and Application of CAD Systems (CADSM), pp. 24-28.
    https://doi.org/10.1109/CADSM52681.2021
  11. Karavay M., Hahanov V., Litvinova E., Khakhanova H. and Hahanova I. (2019), "Qubit Fault Detection in SoC Logic," 2019 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, pp. 1-7.
    https://doi.org/10.1109/EWDTS.2019.8884475
  12. Hahanov V. (2018), Cyber Physical Computing for IoT-driven Services, New York: Springer.
    https://doi.org/10.1007/978-3-319-54825-8
  13. Hahanov V., Litvinova E., Shevchenko O., Chumachenko S., Khakhanova H. and Hahanov I. (2022), "Vector Models for Modeling Logic Based on XOR-Relations," 2022 IEEE 16th International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET), pp. 823-828.
    https://doi.org/10.1109/TCSET55632.2022.9766894
  14. Biercuk M.J., Stace T.M. (2022), “Quantum Computing’s Achilles. Unavoidable errors and how to fix them,” IEEE Spectrum, pp. 28–33.
    https://doi.org/10.1109/MSPEC.2022.9819881
  15. Versluis R., Hagen C. (2020), "Quantum computers scale up: Constructing a universal quantum computer with a large number of qubits will be hard but not impossible," IEEE Spectrum, vol. 57, no. 4, pp. 24-29.
    https://doi.org/10.1109/MSPEC.2020.9055969
  16. Darbinyan K., Harutyunyan G., Shoukourian S., Vardanian V. and Zorian Y. (2011), "A Robust Solution for Embedded Memory Test and Repair," 2011 Asian Test Symposium, pp. 461-462.
    https://doi.org/10.1109/ATS.2011.98
  17. Harutunvan G., Vardanian V.A. and Zorian Y. (2005), "Minimal March tests for unlinked static faults in random access memories," 23rd IEEE VLSI Test Symposium (VTS'05), pp. 53- 59.
    https://doi.org/10.1109/VTS.2005.56
  18. Psarakis M., Gizopoulos D., Paschalis A. and Zorian Y., (2000),"Sequential fault modeling and test pattern generation for CMOS iterative logic arrays," IEEE Transactions on Computers, vol. 49, no. 10, pp. 1083-1099.
    https://doi.org/10.1109/12.888044
  19. Renovell M., Portal J.M., Figueras J. and Zorian Y. (1998), "RAM-based FPGAs: a test approach for the logic," Proceedings Design, Automation and Test in Europe, pp. 82-88.
    https://doi.org/10.1109/DATE.1998.655840
  20. Reinsalu U., Raik J., Ubar R. and Ellervee P. (2011), "Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations," 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver, BC, pp. 164-170.
    https://doi.org/10.1109/DFT.2011.42
  21. Ubar R., Devadze S., Raik J. and Jutman A., (2010), "Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits," 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications, Ho Chi Minh City, pp. 14-19.
    https://doi.org/10.1109/DELTA.2010.32
  22. Reinsalu U., Raik J. and Ubar R. (2010), "Register-transfer level deductive fault simulation using decision diagrams," 2010 12th Biennial Baltic Electronics Conference, pp. 193-196.
    https://doi.org/10.1109/BEC.2010.5631842
  23. Pomeranz I. and Reddy S.M. (2008), "Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 137-146.
    https://doi.org/10.1109/TCAD.2007.907000
  24. Pomeranz I. and Reddy S.M., "Test data compression based on output dependence," 2003 Design, Automation and Test in Europe Conference and Exhibition, pp. 1186-1187, 2003.
    https://doi.org/10.1109/DATE.2003.1253793
  25. Joe J., Mukherjee N., Pomeranz I. and Rajski J. (2022), "Fast Test Generation for Structurally Similar Circuits," 2022 IEEE 40th VLSI Test Symposium (VTS), 1-7.
    https://doi.org/10.1109/VTS52500.2021.9794232
  26. Armstrong D.B. (1972), "A Deductive Method for Simulating Faults in Logic Circuits," IEEE Transactions on Computers, vol. C-21, no. 5, pp. 464-471.
    https://doi.org/10.1109/T-C.1972.223542

Full text: PDF