V.K. Dobrovolskyi, Ph.D., independent CPU architect
(Kyiv, Ukraine, тел. (+38) 0982798517; e-mail:
Èlektron. model. 2019, 41(6):77-90
https://doi.org/10.15407/emodel.41.06.077
ABSTRACT
A project of the new RISC microprocessor architecture is proposed on the basis of the minimal hardware principle (the MHP RISC processor) targeted on effective parallelization. The notion of instruction group is postulated which is formed by the smart compiler. The header instruc-tion of the group points out how many instructions should be issued in parallel. The concept of the flux as a composite of instruction stream and data flow, supported by certain flux hardware, and used for parallelization on higher levels is developed. Formats of typical instructions and their usage are explained on examples. A new method for the loop control which is applicable to loops with the increasing/decreasing numeric loop variable, and also, a new method for the branch parallelization are proposed. The proposed architecture does not contain simultaneous multithreading, register renaming, instruction reordering, out-of-order execution, speculative execution, superscalar execution, delayed branch, branch prediction which all require much hardware. These all are substituted by the notion of instruction group, concept of flux, special instructions, and strong compiler support.
KEYWORDS
microprocessor, parallelism, comparisons, loop control, branch parallelization.
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