SAPOZHNIKOV V.V., SAPOZHNIKOV Vl. V., YEFANOV D.V.
ABSTRACT
The paper presents the results of studying the codes with summation of the weighted data bits under the condition of preservation of the number of check bits, similar to the classical Berger codes. Classes of codes which possess the main properties of the Berger codes and have the least number of undetectable errors in data bits (among known codes) are defined.
KEYWORDS
functional control, undetectable error, weight data bit, code Berger, weighted summation code, tester, generator.
REFERENCES
1. Berger, J.M. (1961), “А note on Error Detecting Codes for Asymmetric Channels”, Information and Control, Vol. 4, no. 1, pp. 68-73.
2. Freiman, C.V. (1962), “Optimal Error Detection Codes for Completely Asymmetric Binary”, Ibid., Vol. 5, no. 1, pp. 64-71.
3. Pradhan, D.K. (1996), Fault-Tolerant Computer System Design, Prentice Hall, N-Y, USA.
4. Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (1992), Samoproveryaemye diskretnye ustroystva [Self-checking discrete devices], Energoatomizdat, St. Petersburg, Russia.
5. Goessel, M. and Graf, S. (1994), Error Detection Circuits, McGraw-Hill, London, UK.
6. Lala, P.K. (2001), Self-Checking and Fault-Tolerant Digital Design, Morgan Kaufmann Publishers, San Francisco, USA.
7. Fujiwara, E. (2006), Code Design for Dependable Systems: Theory and Practical Applications, John Wiley & Sons.
8. Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2010), “The properties of the code with summation in functional control circuits”, Avtomatika i telemekhanika, no. 6, pp. 155-162.
9. Blyudov, A.A., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2012), “A modified summation code for organizing control of combinatorial circuits”, Ibid., no. 1, pp. 169-177.
10. Blyudov, A., Efanov, D., Sapozhnikov, V. and Sapozhnikov Vl. (2012), “Properties of Сode with Summation for Logical Circuit Test Organization”, Proc. of the 10th IEEE East-West Design & Test Symposium (EWDTS'2012), Kharkov, Ukraine, September 14-17, 2012, pp. 114-117.
11. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2012), “Formation of the Berger modified code with minimum number of undetectable errors of informational bits”, Elektronnoe modelirovanie, Vol. 34, no. 6, pp. 17-29.
12. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2013), “Codes with summation to organize the control of combinatorial circuits”, Avtomatika i telemekhanika, no. 6, pp. 153-164.
13. Bose, B. and Lin, D.J. (1985), “Systematic Unidirectional Error-Detection Codes”, IEEE Trans. Comput., Vol. C-34, pp. 1026-1032.
14. Das, D., Touba, N.A., Seuring, M. and Gossel, M. (2000), “Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes”, Proc. of the 6th IEEE International On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3-5, 2000, pp. 171-176.
15. Efanov, D., Sapozhnikov, V., Sapozhnikov, Vl. and Blyudov, A. (2013), “On the Problem of Selection of Code with Summation for Combinational Circuit Test Organization”, Proc. of the 11th IEEE East-West Design & Test Symposium (EWDTS'2013), Rostov-on-Don, Russia, Sept. 27-30, 2013, pp. 261-266.
16. Das, D. and Touba, N.A. (1999), “Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits”, Proc. of the 17th IEEE VLSI Test Symposium, USA, CA, Dana Point, April 25-29, 1999, pp. 370-376.
17. Ghosh, S., Lai, K.W., Jone, W.B. and Chang, S.C. (2004), “Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits”, Proc. of the 13th Asian Test Symposium, Taiwan, Kenting, Nov. 15-17, 2004, pp. 210-215.
18. Favalli, M. and Metra, C. (2001), “Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors”, Design, Automation and Test in Europe (DATE), March 13-16, 2001, pp. 290-296.
19. Ghosh, S. (2004), “Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits”, Master's thesis, Dept. of ECECS, University of Cincinnati, Cincinnati, Ohio, USA, May, 2004.
20. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V. and Nikitin, D.A. (2013), “Method of constructing the Berger code with high error detecting efficiency in information bits”, Elektronnoe modelirovanie, Vol. 35, no. 4, pp. 21-34.
21. Sapozhnikov, V.V., Morozov, A., Sapozhnikov, Vl.V. and Goessel, M. (1998), “A New Design Method for Self-Checking Unidirectional Combinational Circuits”, J. of Electronic Testing: Theory and Applications, Vol. 12, no. 2, pp. 41-53.
22. Matrosova, A.Yu., Ostanin, S.A. and Singkh, V. (2013), “Detection of minor ways of logic circuits based on the joint analysis of the AND-OR trees and SSBDD-graphs”, Avtomatika i telemekhanika, no. 7, pp. 126-142.
23. Melnikov, A.G., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (1986), “Synthesis of self-checking testers for codes with the summation”, Problemy peredachi informatsii, Vol. XXII, no. 2, pp. 85-97.
24. Marouf, M.A. and Friedman, A.D. (1978), “Design of Self-Checking Checkers for Berger Codes”, Proc. of the 8th Annual Intern. Conf. on Fault-Tolerant Computing, Toulouse, France, 1978, pp. 179-183.
25. Piestrak, S.J. (1995), Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Oficyna Wydawnicza Politechniki Wroclavskiej, Wroclaw, Poland.