V.V. Sapozhnikov, Vl.V. Sapozhnikov, D.V. EfanovV.V. Sapozhnikov, Vl.V. Sapozhnikov, D.V. Efanov
Èlektron. model. 2018, 38(6):25-44
https://doi.org/10.15407/emodel.38.06.025
ABSTRACT
The new approach to concurrent error detection system organization with provision of property of totally self-checking structure based on Boolean complement method by constant-weight code “1-out-of-3” is offered in the paper. This approach is based on distinguishing the groups of outputs of tested device (three unidirectionally independent outputs in each) meeting the requirements of monotonous independence with their further test using “1-out-of-3” constant-weight code and unification of outputs of certain testers at the exits of self-checking comparator. Formulas of complement functions calculation are adduced; they allow providing the complex of test combinations for “1-out-of-3” code checker as well as for all XOR gates in Boolean complement block structure. Conditions providing totally self-checking of the structure are declared.
KEYWORDS
concurrent error detection system, Boolean complement, constant-weight code, totally self-checking structure, checking, structural redundancy.
REFERENCES
1. Sogomonyan, E.S. and Slabakov, E.V. (1989), Samoproveryaemye ustroystva i otkazoustoychivye sistemy [Self-checking devices and failover systems], Radio i svyaz, Moscow, Russia.
2. Nicolaidis, M. and Zorian, Y. (1998), On-line testing for VLSI – a compendium of approaches, Journal of electronic testing: theory and applications, no. 12, pp. 7-20.
3. Mitra, S. and McCluskey, E.J. (2000), Which concurrent error detection scheme to choose?”, Proceedings of International Test Conference 2000, USA, Atlantic City, NJ, October 03-05, 2000, pp. 985-994.
4. Sapozhnikov, V.V. et al. (2002), “Organization of functional checking of combinational circuits by the logic complement method”, Elektronnoe modelirovanie, Vol. 24, no. 6, pp. 52- 66.
5. Goessel, M., Morozov, A.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2003), “Logic complement, a new method of checking the combinational circuits”, Avtomatika i telemekhanika, no. 1, pp. 167-176.
6. Parkhomenko, P.P. and Sogomonyan, E.S. (1981), Osnovy tekhnicheskoy diagnostiki (optimizatsiya algoritmov diagnostirovaniya, apparaturnye sredstva) [Basics of technical diagnostics (optimization of diagnostic algorithms and equipment)], Energoatomizdat, Moscow,
Russia.
7. Goessel, M., Sapozhnikov, Vl., Saposhnikov, V. and Dmitriev, A. (2000), “A new method for concurrent checking by use of a 1-out-of-4 code”, Proceedings. of the 6th IEEE International On-line Testing Workshop, July 3-5, 2000, Palma de Mallorca, Spain, pp. 147-152.
https://doi.org/10.1109/OLT.2000.856627
8. Morozov, A., Sapozhnikov, V.V., Saposhnikov, Vl.V. and Goessel, M. (2000), “New selfchecking circuits by use of Berger-codes”, Proceedings. of the 6th IEEE International On-line Testing Workshop, July 3-5, 2000, Palma de Mallorca, Spain, pp.171-176.
9. Sapozhnikov, V.V. et al. (2004), “Design of totally self-checking combinational circuits by use of complementary circuits”, Proceedings of East-West Design & Test Workshop, Yalta, Ukraine, 2004, pp. 83-87.
10. Goessel, M., Morozov, A.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2005), “Checking combinational circuits by the method of logic complement”, Avtomatika i telemekhanika, no. 8, pp. 161-172.
https://doi.org/10.1007/s10513-005-0174-2
11. Göessel, M., Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New methods of concurrent checking: Edition 1, Springer Science+Business Media B.V., Dodrecht, the Netherlands.
12. Sen, S.K. (2010), “A self-checking circuit for concurrent checking by 1-out-of-4 code with design otimization using constraint don’t cares”, National Conf. on Emerging trends and advances in Electrical Engineering and Renewable Energy (NCEEERE 2010), Sikkim Manipal Institute of Technology, Sikkim, December 22-24, 2010.
13. Das, D.K., Roy, S.S., Dmitiriev, A., Morozov, A. and Göessel,M. (2012), “Constraint don’t cares for optimizing designs for concurrent checking by 1-out-of-3 codes”, Proceedings of the 10th International Workshops on Boolean Problems, Freiberg, Germany, September 2012, pp. 33-40.
14. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2016), “Method of logical devices concurrent error detection system based on “2-out-of-4” code”, Izvestiya vuzov. Priborostroenie, Vol. 59, no. 7, pp. 524-533. DOI 10.17586/0021-3454-2016-59-7-524-533.
15. Sapozhnikov, V., Sapozhnikov, Vl. and Efanov, D. (2015), “Concurrent error detection of combinational circuits by the method of Boolean complement on the base of «2-out-of-4» code”, Proceedings of the 14th IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, October 14-17, 2016, pp. 126-133.
16. Lala, P.K. (2007), Self-checking and fault-tolerant digital design, Morgan Kaufmann Publishers, San Francisco, USA.
17. Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (1991), “About synthesis of self-checking checkers for 1-out-of-3 code”, Avtomatika i telemekhanika, no. 2, pp. 178-188.
18. Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (1992), Samoproveryaemye diskretnye ustroystva [Self-checking discrete devices], Energoatomizdat, St. Petersburg, Russia.
19. Aksyonova, G.P. (1979), “Necessary and sufficient conditions for the design of totally checking circuits of compression by modulo 2”, Avtomatika i telemekhanika, no. 9, pp. 126-135.
20. Busaba, F.Y. and Lala, P.K. (1994), “Self-checking combinational circuit design for single and unidirectional multibit errors”, Journal of electronic testing: theory and applications, Vol. 5, Iss. 5, pp. 19-28.
https://doi.org/10.1007/BF00971960
21. Sapozhnikov, V.V., Morozov, A., Sapozhnikov, Vl.V. and Göessel, M. (1998), “A new design method for self-checking unidirectional combinational circuits”, Journal of electronic testing: theory and applications, Vol. 12, Iss. 1-2, pp. 41-53.
22. Goessel, M., Morozov, A.A., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (1997), “Investigation of combination self-testing devices having independent and monotonously independent outputs”, Avtomatika i telemekhanika, no. 2, pp. 180-193.
23. David, R. (1978), “Totally self-checking 1-out-of-3 checker”, IEEE Transactions on Computers, Vol. C-27, pp. 570-572.
https://doi.org/10.1109/TC.1978.1675149
24. Golan, P. (1984), “Design of totally self-checking checker for 1/3 code”, IEEE Transactions on Computers, Vol. 33, p. 285.
25. Lo, J. and Thanawastien, S. (1990), “On the design of combinational totally self-checking 1/3 code checkers”, IEEE Transactions on Computers, Vol. 39, pp. 387-393.
https://doi.org/10.1109/12.48869
26. Paschalis, A., Gaitanis, N., Gizopoulos, D. and Kostarakis, P. (1998), “A totally self-checking 1-out-of-3 code error indicator”, Journal of electronic testing: theory and application, Vol. 13, Iss.1, pp. 61-66.
https://doi.org/10.1023/A:1008341301415
27. Collection of digital design Benchmarks, available at: http://ddd.fit.cvut.cz/prj/Benchmarks/.
28. Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P.R., Brayton, R.K. and Sangiovanni-Vincentelli, A. (1992), SIS: A system for sequential circuit synthesis, Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA.
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