A.M. Sergiyenko, V.P. Simonenko
ABSTRACT
Methods for the synchronous dataflow graph (SDF) retiming, and mapping it into pipelined datapaths are considered. A method of retiming the spatial SDF is proposed. The method is based on the SDF representation in the multidimensional space. The dimensions of this space are spatial coordinate of the processing unit, coordinate of the operator firing, and operator type. At the first stage of the datapath synthesis the operator nodes are placed in the space according to a set of rules and theorems providing the minimum hardware volume and minimum clock period for the given number of clock periods in the algorithm cycle. At the second stage of the synthesis this spatial SDF is balanced and optimized providing the minimum register and multiplexor number in the resulting datapath. The resulting spatial SDF is described in VHDL language and is modeled and compiled using proper CAD tools. The method is successfully proven by the synthesis of a set of infinite impulse response filters for FPGA.
KEYWORDS
retiming, synchronous dataflow, scheduling, pipelining, folding, datapath.
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