Electronic modeling

Vol 42, No 2 (2020)

https://doi.org/10.15407/emodel.42.02

CONTENTS

Computational Processes and systems

  SAPOZHNIKOV V.V., SAPOZHNIKOV V.Vl., EFANOV D.V.
Fault Detection in CombinationalLogic Circuits Based on Symmetrically Independent Outputs Groups Checking


3-24
  SERGIYENKO A. M., ROMANKEVICH V. A., SERHIENKO A. A.
Genetic Programming ofApplication-Specific Pipelined Datapaths


25-40
  SHEVCHENKO S.S., SHEVCHENKO O.S.
Determination of the Natural Frequencies of the Centrifugal Machine Rotor with a System of Automatic Balancing of Axial Forces

41-58

Application of Modeling Methods and Facilities

  ZUBARIEV D.O., SKARGA-BANDUROVA I.S., SAPYTSKA O.M.
Efficiency Analysis ofthe Image Optimization Algorithm for the Formation of a Database Not Confirmedby the User


59-68
  MARUSENKOVA T.A.
SPICE Model of a Logarithmic Converter for Magnetic Tracking Systems


69-90
  FARHADZADE E.M., MURADALIYEV A.Z.,RAFIYEVA T.K.,RUSTAMOVA A.A.
Branchmarkinq Power Units Tps


91-109
  SAVKA N.Ya.
Artificial Neural Networks for Modeling of Crisis Management of National Economy


109-120
  PODHURENKO V.S.,GETMANETS O.M., TEREKHOV V.E.
Mathematical Model of Wind Turbine Electricity Production As a Method of Increasing its Efficiency


121-127

 

FAULT DETECTION IN COMBINATIONAL LOGIC CIRCUITS BASED ON SYMMETRICALLY INDEPENDENT OUTPUTS GROUPS CHECKING

V.V. Sapozhnikov, V.Vl. Sapozhnikov, D.V. Efanov

Èlektron. model. 2020, 42(2):03-24
https://doi.org/10.15407/emodel.42.02.003

ABSTRACT

The main study results of the testing methods development for combinational circuits based on the properties of the codes focused on the errors detection of certain types and multiplicities are described. It is established that when using classical sum codes (Berger's code) and a number of their modifications when organizing checking of combinational circuits, it is possible to use the features of detecting unidirectional and some non-unidirectional errors in data vectors. It is shown that it is possible to search for such output’s groups on which only symmetrical errors occur due to single-error of the circuit internal structural elements. Such output groups are called symmetrically independent (SI-groups) outputs. The combinational circuit outputs group belonging conditions to the outputs SI-groups are determined. It is shown that each outputs SI-group can be controlled using a separate check subsystem based on a code with the detection of any asymmetric errors (and any asymmetric errors to certain multiplicities). Methods are proposed for searching for outputs SI-groups in combinational circuits organizing control. Particular attention is paid to the faults control at the combinational circuit’s inputs.

KEYWORDS

combinational circuit, self-checking structure, unidirectional, symmetrical, asymmetrical errors, symmetrically-independent outputs groups.

REFERENCES

  1. Fujiwara, E. (2006), Code Design for Dependable Systems: Theory and Practical Applications, John Wiley & Sons, New Jersey, USA.
    https://doi.org/10.1002/0471792748
  2. Ubar, R., Raik, J. and Vierhaus, H.T. (2011), Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source), IGI Global, New York, USA.
    https://doi.org/10.4018/978-1-60960-212-3
  3. Göessel, M., Ocheretny, V., Sogomonyan, E. and Marienfeld, D. (2008), New Methods of Concurrent Checking: Edition 1, Springer Science+Business Media B.V, Dordrecht, Netherland.
  4. Nicolaidis, M. and Zorian, Y. (1998), “On-Line Testing for VLSI – А Compendium of Approaches”, Journal of Electronic Testing: Theory and Applications, no. 12, pp. 7-20. DOI: 10.1023/A:1008244815697.
    https://doi.org/10.1023/A:1008244815697
  5. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Yefanov, D.V. (2015) “Classification of errors in information vectors of systematic codes”, Izvestiya Vysshikh Uchebnykh Zavedeniy. Priborostroenie, Vol. 58, no. 5, pp. 333-343. DOI 10.17586/0021-3454-2015-58-5-333-343.
    https://doi.org/10.17586/0021-3454-2015-58-5-333-343
  6. Dmitriyev, V.V., Yefanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2018), “Sum Codes with Efficient Detection of Twofold Errors for Organization of Concurrent Error-Detection Systems of Logical Devices”, Avtomatika i telemekhanika, no. 4, pp. 105-122.
    https://doi.org/10.1134/S0005117918040082
  7. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Yefanov, D.V. and Dmitriyev, V.V. (2017), “New structures of the concurrent error detection systems for logic circuits”, Avtomatika i telemekhanika, no. 2, pp. 127-143.
    https://doi.org/10.1134/S0005117917020096
  8. Ghosh, S., Basu, S. and Touba, N.A. (2005), “Synthesis of Low Power CED Circuits Based on Parity Codes”, Proceeding of the 23rd IEEE VLSI Test Symposium (VTS'05), pp. 315-320.
    https://doi.org/10.1109/VTS.2005.80
  9. Freiman, C.V. (1962), “Optimal Error Detection Codes for Completely Asymmetric Binary Channels”, Ibid, Vol. 5, Issue. 1, pp. 64-71. DOI: 1016/S0019-9958(62)90223-1.
    https://doi.org/10.1016/S0019-9958(62)90223-1
  10. Berger, J.M. (1961), “A Note on Error Detection Codes for Asymmetric Channels”, Information and Control, Vol. 4, Issue. 1, pp. 68-73. DOI: 10.1016/S0019-9958(61)80037-5.
    https://doi.org/10.1016/S0019-9958(61)80037-5
  11. Piestrak, S.J. (1995), Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Oficyna Wydawnicza Politechniki Wrocłavskiej, Wrocław, Poland.
  12. Das, D., Touba, N.A., Seuring, and Gossel, M. (2000), “Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes”, Proceeding of IEEE 6th International On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3-5, 2000, pp. 171-176. DOI: 10.1109/OLT.2000.856633.
    https://doi.org/10.1109/OLT.2000.856633
  13. Efanov, D., Sapozhnikov, V. and Sapozhnikov, Vl. (2017) “Generalized Algorithm of Building Summation Codes for the Tasks of Technical Diagnostics of Discrete Systems”, Proceeding of the 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29 - October 2, 2017, pp. 365-371. DOI: 1109/EWDTS. 2017.8110126.
    https://doi.org/10.1109/EWDTS.2017.8110126
  14. Sogomonyan, E.S. and Slabakov, E.V. (1989), Samoproveryayemyye ustroystva i otkazoustoychivyye sistemy [Self-checking devices and failover systems], Radio & Svjaz`, Moscow, USSR.
    https://doi.org/10.1007/BF00971975
  15. Gessel', M. and Sogomonyan, Ye.S. (1992), Design of self-testing and self-checking combinational circuits with weakly independent outputs”, Avtomatika i telemekhanika, no. 8, pp. 150-
  16. Sogomonyan, E.S. and Gössel, M. (1993) “Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs”, Journal of Electronic Testing: Theory and Applications, Vol. 4, Issue. 4, pp. 267-281. DOI:10.1007/
  17. Busaba, F.Y. and Lala, P.K. (1994), “Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors”, Journal of Electronic Testing: Theory and Applications, Issue. 5, pp. 19-28. DOI: 1007/BF00971960.
    https://doi.org/10.1007/BF00971960
  18. Morosow, A., Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Goessel, M. (1998), “Self-Checking Combinational Circuits with Unidirectionally Independent Outputs”, VLSI Design, Vol. 5, Issue. 4, pp. 333-345. DOI: 10.1155/1998/20389.
    https://doi.org/10.1155/1998/20389
  19. Yefanov, D.V., Sapozhnikov, V.V., Sapozhnikov, Vl.V. (2018), “Synthesis of Self-Checking Combinational Devices Based on Allocating Special Groups of Outputs”, Avtomatika i telemekhanika, no. 9, pp. 79-94.
    https://doi.org/10.1134/S0005117918090060
  20. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and Efanov, D.V. (2018), Kody Khemminga v sistemakh funktsional'nogo kontrolya logicheskikh ustroystv [Hamming codes in concurrent error detection systems of logic devices], Nauka, St. Petersburg, Russia.
  21. Das, D. and Touba, N.A. (1999), “Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes”, Journal of Electronic Testing: Theory and Applications, Vol. 15, Issue. 1-2, pp. 145-155. DOI: 10.1023/A:1008344603814.
    https://doi.org/10.1023/A:1008344603814
  22. Yefanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2015), “Applications of Modular Summation Codes to Concurrent Error Detection Systems for Combinational Boolean Circuits”, Avtomatika i telemekhanika, no. 10, pp. 152-169.
    https://doi.org/10.1134/S0005117915100112
  23. Prokof'yev, A.A., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (1984), Logical method for electrical mounting testing”, Elektronnoje Modelirovanije, Vol. 6, no. 4, pp. 55-59.
  24. Sapozhnikov, V., Sapozhnikov, Vl. and Efanov, D. (2017), “Search Algorithm for Fully Tested Elements in Combinational Circuits, Controlled on the Basis of Berger Codes”, Proceeding of the 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29 - October 2, 2017, pp. 99-108. DOI: 10.1109/EWDTS. 2017.8110085.
    https://doi.org/10.1109/EWDTS.2017.8110085
  25. Yefanov, D.V., Sapozhnikov, V.V. and Sapozhnikov, Vl.V. (2017), “Conditions for Detecting a Logical Element Fault in a Combination Device under Concurrent Checking Based on Berger`s Code”, Avtomatika i telemekhanika, no. 5, pp. 152-165.
    https://doi.org/10.1134/S0005117917050113

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GENETIC PROGRAMMING OF APPLICATION-SPECIFIC PIPELINED DATAPATHS

A.М. Sergiyenko, V.A. Romankevich, A.A. Serhienko

Èlektron. model. 2020, 42(2):25-40
https://doi.org/10.15407/emodel.42.02.025

ABSTRACT

A method for the synthesis of application-specific pipeline data paths based on the genetic programming is proposed. The method consists in representing the algorithm with a spatial synchronous data flow graph, encoding its matrix of operator-nodes as chromosomes and using the genetic optimization algorithm. The high efficiency of the method is shown by the example of the discrete cosine transform processor synthesis, which is configured in FPGA.

KEYWORDS

FPGA, VHDL, SDF, data flow graph, genetic programming.

REFERENCES

  1. Bhattacharyya, S. and Wolf, M. (2016), Tools and Methodologies for System-Level Design. Electronic Design Automation for IC System Design, Verification, and Testing, CRC Press.
    https://doi.org/10.1201/b19569-3
  2. Wang, G., Gong, W. and Kastner, R. (2008), Operation Scheduling: Algorithms and Applications. High-level synthesis: from algorithm to digital circuit,
  3. Hwang, C.T., Lee, T.H. and Hsu, Y.C. (1991), “A formal approach to the scheduling prob­lem in high level synthesis”, IEEE Trans. Comput. Aided Design, 10, no. 4, pp. 464-475.
    https://doi.org/10.1109/43.75629
  4. Kruse, R., Borgelt, C., Braune, C., Mostaghim, S. and Steinbrecher, M. (2016), Computational Intelligence. A Methodological Introduction. 2-nd Ed, Springer.
    https://doi.org/10.1007/978-1-4471-7296-3
  5. Miller, F. (2011), Cartesian Genetic Programming, Springer, Berlin, Germany.
    https://doi.org/10.1007/978-3-642-17310-3
  6. Sergiyenko, A. M. and Simonenko, V. P. (2007), “Mapping periodic algorithms to programmable logic integrated circuits”, Electronic Modeling, 29. no. 2, pp. 49-61.
  7. Sergiyenko, A.M. and Simonenko, V.P. (2016), “Sheduling of Synchronous Data Flows”, System Investigations and Informational Technologies, no. 1, pp. 51-62. DOI: 10.20535/ 2308-8893.2016.1.06
    https://doi.org/10.20535/SRIT.2308-8893.2016.1.06
  8. Affenzeller, M., Winkler, S., Wagner, S. and Beham, A. (2009), Genetic Algorithms and Genetic Programming. Modern Concepts and Practical Applications, Chapman & Hall, CRC Press.
    https://doi.org/10.1201/9781420011326
  9. Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M. and Vemuri, R. (1998), “An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures”, Proceeding of the Reconfigurable Architectures Workshop (RAW’98), Springer, LNCS, Vol. 1388, Berlin, Heidelberg, pp. 31-36.
    https://doi.org/10.1007/3-540-64359-1_669
  10. Grajcar, M. (2000), “Conditional Scheduling for Embedded Systems using Genetic List Scheduling”, Proceeding of the 13th International Symposium on System Synthesis (ISSS), Madrid, Spain, 2000, pp. 123-128.
    https://doi.org/10.1109/ISSS.2000.874038
  11. Parsa, S. and Lotfi, S. (2006), “A New Genetic Algorithm for Loop Tiling”, The Journal of Supercomputing, Vol. 37, no. 3, pp. 249-269.
    https://doi.org/10.1007/s11227-006-6367-9
  12. Bonsma, E. and Gerez, S. (1997), “A genetic approach to the overlapped scheduling of iterative data-flow graphs for target architectures with communication delays”, ProRISC Workshop on Circuits, Systems and Signal Processing, November 27-28, 1997, Mierlo, Netherlands, pp. 67-76.
  13. Mandal, C., Chakrabarti, P. and Ghose, S. (1996), “Design space exploration for data path synthesis”, Proceeding  of  the  10-th  International  Conference  on  VLSI  Design,  1996, pp. 166-170.
  14. Mandal, С., Chakrabarti, P. and Ghose, S.(2000), “GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths”, IEEE Trans. on VLSI Systems, 8, no. 6, pp. 747-750.
    https://doi.org/10.1109/92.902270
  15. Grewal, G., O’Cleirigh, M. and Wineberg, M. (2003), “An evolutionary approach to behavioural-level synthesis”, The 2003 Congress on Evolutionary Computation, (CEC’03), 1, pp. 264-272.
    https://doi.org/10.1109/CEC.2003.1299584
  16. Chen, D. and Cong, J. (2004), “Register binding and port assignment for multiplexer optimization”, Proceeding of the 2004 Conference on Asia South Pacific Design Automation, (ASP-DAC’04), 68-73.
    https://doi.org/10.1109/ASPDAC.2004.1337542
  17. Krishnan, V. and Katkoori, S. (2006), “A genetic algorithm for the design space exploration of datapaths during high-level synthesis”, IEEE Trans. Evolutionary Computation, Vol. 10, no. 3, pp. 213-229.
    https://doi.org/10.1109/TEVC.2005.860764
  18. Ferrandi, F., Lanzi, P.L., Palermo, G., Pilato, C., Sciuto, D. and Tumeo, A. (2007), “An evolutionary approach to area-time optimization of FPGA designs”, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, (ICSAMOS), pp. 145-152.
    https://doi.org/10.1109/ICSAMOS.2007.4285745
  19. Palesi, M. and Givargis, T. (2002), “Multi-objective design space exploration using genetic algorithms”, International Conference on Hardware/software Codesign, (CODES), ACM, New York, USA, pp. 67-72.
    https://doi.org/10.1145/774789.774804
  20. Pilato, C., Tumeo, A., Palermo, G., Ferrandi, F., Lanzi, P. L. and Sciuto, D. (2008), “Improving evolutionary exploration to area-time optimization of FPGA designs”, Journal of Systems Architecture, 54, pp. 1046-1057.
    https://doi.org/10.1016/j.sysarc.2008.04.010
  21. Poli, R. (1997), “Evolution of Graph-like Programs with Parallel Distributed Genetic Programming”, Genetic Algorithms: Proceeding of the 7-th International Conference, pp. 346-
  22. Miller, J.F., Walker, J.A. (2006), “Embedded cartesian genetic programming and the lawnmower and hierarchical-if-and-only-if problems”, Genetic and Evolutionary Computation Conference, GECCO06, Seattle, Washington, USA, July, 2006, pp. 911-918.
  23. Parhi, K. K. (1999), VLSI Digital Signal Processing Systems. Design and Implementation, Wiley.
  24. Husa, J. and Kalkreuth, R. (2018), “A Comparative Study on Crossover in Cartesian Genetic Programming”, Proceeding of the 21-st European Conference “Genetic Programming”, EuroGP, Parma, Italy, April 4-6, 2018, Vol. 10781, pp. 203-219.
    https://doi.org/10.1007/978-3-319-77553-1_13
  25. Koncal, O. and Sekanina, L. (2019), “Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming”, Proceeding of the 22-nd European Conference in Genetic Programming, EuroGP, Leipzig, Germany, April 24-26, 2019, pp. 98-113.
    https://doi.org/10.1007/978-3-030-16670-0_7
  26. Horn, J., Nafpliotis, N. and Goldberg, D.E. (1994), “A Niched Pareto Genetic Algorithm for Multiobjective Optimization”, Proceeding of the 1-st IEEE Conf. on Evolutionary Computation, Vol. 1, pp. 82-87.
    https://doi.org/10.1109/ICEC.1994.350037
  27. Holland, J. H. (1992), Adaptation in Natural and Artificial Systems, MIT Press, USA.
    https://doi.org/10.7551/mitpress/1090.001.0001
  28. Petrowski, A. and Ben-Hamida, S. (2017), Evolutionary Algorithms, Wiley & Sons, Inc, Hoboken, New Jersey, USA.
    https://doi.org/10.1002/9781119136378
  29. Lee, S., Soak, S., Kim, K., Park, H. and Jeon, M. (2008), “Statistical properties analysis of real world tournament selection in genetic algorithms”, Applied Intelligence, 28, no. 2, pp. 195-205.
    https://doi.org/10.1007/s10489-007-0062-2
  30. Sergiyenko, A., Serhienko, A. and Simonenko, A. (2017), “A method for synchronous dataflow retiming”, IEEE First Ukraine Conference on Electrical and Computer Enginee­ring (UKRCON), Kiev, Ukraine, 2017, pp. 1015-1018.
    https://doi.org/10.1109/UKRCON.2017.8100404
  31. Chao, L., LaPaugh, A. and Sha, E. (1993), “Rotation scheduling: A loop pipelining algorithm” Proceeding of the  30-th Design Automation Conference. (DAC’93), June 1993, pp. 566-572.
    https://doi.org/10.1145/157485.165042
  32. Jin, Y. (2005), “A comprehensive survey of fitness approximation in evolutionary computation”, Soft Computing,   9, no. 1, pp. 3-12.
    https://doi.org/10.1007/s00500-003-0328-5
  33. Norenkov, I.P. (2009), Osnovy Avtomatizirovannogo Proektirovaniya [Computer Aided Design Basics], Izd-vo MGTU im. Baumana, Мoskow, Russia.
  34. Nikara, J., Takala, J., Akopian, D. and Saarinen, J. (2001), “Pipeline Architecture for DCT/IDCT”, IEEE International Symposium on Circuits and Systems, (ISCAS 2001), May 6-9, Sydney, Australia, pp. 902-905.
    https://doi.org/10.1109/ISCAS.2001.922384
  35. Hsiao, S.-F., Shiue, W.-R. and Tseng, J.-M. (1991), “A cost efficient fully-pipelinable architecture for DCT/IDCT”, IEEE Trans. On Communications, Vol. 39, no. 5, pp. 640-643.

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DETERMINATION OF THE NATURAL FREQUENCIES OF THE CENTRIFUGAL MACHINE ROTOR WITH A SYSTEM OF AUTOMATIC BALANCING OF AXIAL FORCES

S.S. Shevchenko, O.S. Shevchenko

Èlektron. model. 2020, 42(2):41-58
https://doi.org/10.15407/emodel.42.02.041

ABSTRACT

The model of balancing device thrust of multistage centrifugal machine rotor that performs both functions of hydraulic seal and a radial-thrust hydrostatic bearing was considered. The linearized equations of the centrifugal pump rotor joint radial-axial vibrations with an auto rerelieving system are obtained. Expressions for defining amplitude and phase frequency characteristics are derived.

KEYWORDS

hydraulic seal, axial force balancer, joint radial-axial vibrations, frequency characteristics.

REFERENCES

  1. Martsinkovskiy, V.A. and Shevchenko, S.S. (2018), Nasosy atomnykh elektrostantsiy: raschet, konstruirovaniye, ekspluatatsiya [Pumps of nuclear power plants: calculation, design, operation], Izd-vo «Universitetskaya kniga», Sumy, Ukraine.
  2. Martsinkovsky, V.A. (2009), Osnovy dinamiki rotorov [Fundamentals of the dynamics of rotors], Sumy State University, Sumy, Ukraine.
  3. Martsinkovsky, V.A. (2005), Shchelevyye uplotneniya: teoriya i praktika [Groove seals: theory and practice], Sumy State University, Sumy, Ukraine.
  4. Marcinkowski, W., Korczak, A. and Peczkis, G. (2009), Dynamika zespoółu wirującego pompy odśrodkowej welostopniowej z tarczą odciążającą. Zeszyty naukowe, Nauki techniczne, pp. 245-263.
  5. Korczak, A. (2005), Badania układów równoważących napór osiowy w wielostopniowych pompach odśrodkowych. Gliwice: Wydawnictwo Politechniki Śląskiej, Zeszyt Naukowy nr 1679, seria Energetyka nr 141.
  6. Marcinkowski, W. (2004), “Szczeliny tarczy odciążającej napór osiowy i ich wplyw na dynamikę zespolu wirującego pompy odśrodkowej wielostopniowej/ W. Marcinkowski, A.Korczak”, Proceeding of the X International Conference, Seals and Sealing Technology in Machines and Devices, Wroclaw, Poland, pp. 318-328.
  7. Marcinkowski, W. and Kundera, Cz. (2008), Teoria konstrukcji uszczelnien bez- stykowych.-Kielce, Wyd-wo Politechniki Swiętokrzyskiej.
  8. Drozdovich, V.N. (1976), Gazodinamicheskiye podshipniki [Gas-dynamic bearings], Mashinostroyeniye, Leningrad, USSR.

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Efficiency Analysis of the Image Optimization Algorithm for the Formation of a Database Not Confirmed by the User

D.O. Zubariev, Post-graduate
G.E. Pukhov Institute for Modelling in Energy Engineering
National Academy of Sciences of Ukraine
(15, General Naumov Str., 03164, Kiev, Ukraine,
tel. +380996810567; e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.),
I.S. Skarga-Bandurova, Doct. of Technical Sciences,
O.M. Sapytska, Cand. of Historical Sciences,
Volodymyr Dahl East Ukrainian National University
(59a, Tsentralny pr., 93400, Severodonetsk, Luhansk oblast, Ukraine,
tel. +380645228997; +380664838802;
e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.; This email address is being protected from spambots. You need JavaScript enabled to view it.)

Èlektron. model. 2020, 42(2):59-68
https://doi.org/10.15407/emodel.42.02.059

ABSTRACT

The ultimate goal of any process optimization in a particular area is to save time and human resources. The article analyzes the effectiveness of the original algorithm image processing when sampling for training artificial neural network CNN Class based on User-Confirmed Image-Dataset for needs defining image elements within binary logic.

KEYWORDS

Deep learning, Image-Dataset, image optimization function, network learning algorithm.

REFERENCES

  1. Zubarev, D.O. and Skarga-Bandurova, I.S. (2018), “Analiz efekty`vnosti navchannya CNN za pry`ncy`pom "vchy`tel`-uchen`" z vy`kory`stannyam nepidgotovlenogo Image-Dataset, Visny`k Nacional`nogo texnichnogo universy`tetu «XPI»”, Seriya «Informaty`ka i modelyuvannya», available at: https://doi.org/10.20998/2411-0558.2018.42.10 (Accessed 8 Jan 2019).
    https://doi.org/10.20998/2411-0558.2018.42.10
  2. Goodfellow, I., Bengio, Y., Courville, A. and Bach F. (2017), Deep learning, Cambridge, MA: MIT Press.
  3. Atienza, R. (2018), Advanced Deep Learning with Keras, Packt Publishing, Birmingham, UK.
  4. Nielsen, M. (2018), “Neural Networks and Deep Learning”, available at: http://neuralnetworksanddeeplearning.com (Accessed 15 Jan 2019).
  5. Chollet, F. (2017), Deep Learning with Python,Manning Publications, New York, USA.
  6. Rosebrock, A. (2017), Deep Learning for Computer Vision с Python, PyImageSearch.
  7. Shanmugamani, R. (2018), Deep Learning for Computer Vision Packt, PacktPublishing, Birmingham, UK.
  8. Sejnowski, T. J. (2018), The Deep Learning Revolution, MA: MIT Press.
    https://doi.org/10.7551/mitpress/11474.001.0001
  9. Pejić-Bach, M. (2007), “Developing system dynamics models with «step-by-step» approach”, available at: https://www.researchgate.net/publication/28811323_Developing_ system_dynamics_models_with_step-by-step_approach (Accessed 24 Dec 2018).
  10. Sewak, M., Rezaul K. and Pujari, P. (2018), Practical Convolutional Neural Networks, Packt Publishing.
  11. “OpenCV 2.4.13.7 documentation. Miscellaneous Image Transformations. Adaptive Threshold”, available at: https://docs.opencv.org/2.4/modules/imgproc/doc/miscellaneous_ transformations.html?highlight=threshold#threshold (Accessed 18 Jan 2019).
  12. (2018), “Python Script to download hundreds of images from Google Images”, available at: https://github.com/hardikvasa/google-images-download (Accessed 24 Jan 2019).
  13. Langtangen, H.P. (2015), “Doing operating system tasks in Python”, available at: https://hplgit.github.io/edu/ostasks/ostasks.pdf. (Accessed 26 Jan 2019).
  14. Howse, J. (2013), OpenCV Computer Vision with Python, Packt Publishing, Birmingham, UK.
  15. “The Python Standart Library. Subprocess management”, available at: https:// docs.python.org/2/library/subprocess.html (Accessed 26 Jan 2019).
  16. Gulli, A. and Pal, S. (2017), Deep Learning with Keras, Packt Publishing.
  17. Tosi, S. (2009), Matplotlib for Python Developers, Packt Publishing, Birmingham, UK.
  18. “The Python Standart Library. Parser for command-line options, arguments and sub-commands”, available at: https://docs.python.org/3.7/library/argparse.html (Accessed 26 Jan 2019).
  19. Changhau, I. (2017), “Loss Functions in Neural Networks”, available at: https:// isaacchanghau.github.io/post/loss_functions/ (Accessed 26 Jan 2019).

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