SAUKH S.E.

ABSTRACT

Acolumn, row, column-row and multi-rank methods of updating the factor matrices derived from CR-matrix factorization are proposed. We obtain estimates of the computational complexity of the CR-updating methods. The conditions for their effective use in the Newton iterative method for solving nonlinear algebraic equations are determined. The experimental results of using the CR-updating methods of test matrices for solution of large scale systems of nonlinear equations
are presented.

KEYWORDS

sparse matrices, matrix update, a column-row factorization. 

REFERENCES

1. Dantzig, G.B. and Thapa, M.N. (1997), Linear programming. 1: Introduction, Springer, NY.
2. Cottle,  R.W., Pang, J.-S. and  Stone, R.E. (1992), The Linear Complementarity Problem, SIAM, Philadelphia, USA.
3. Available at: http://www.springerlink.com/content/978-3-540-35447-1#secion=424811&page=1&loсus=13
4. Eldersveld, S.K. and  Saunders, M.A. (1992), “A block-LU update for large-scale linear programming”,  SIAM J. on Matrix Analysis and Applications,  Vol. 13, no.  1, pp. 191-201.
5. Available at: http://www.mcs.anl.gov/uploads/cels/papers/P1565.pdf
6. Tewarson, R.P. and  Zhang, Yin (2005), “Sparse quasi-Newton LU updates”, Intern. J. for Numerical Methods in Engineering, Vol. 24, no.  6, pp. 1093-1100.
7. Saukh, S.Ye. (2007), “Method of CR-matrix factorization of large dimension”,  Elektronnoe modelirovanie, Vol.  29, no. 6, pp. 3-22.
8. Available at: http://www.cise.ufl.edu/research/sparse/matrices/index.html

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SAPOZHNIKOV V.V., SAPOZHNIKOV Vl.V., YEFANOV D.V., NIKITIN L.A.

ABSTRACT

A new class of codes with summation of weighted data bits, has been considered in the paper. A simple ratio of data bits’ weights has been defined; it allows us to construct a more efficient (from the standpoint of detecting errors in the data vectors of the code) method, than the well-known classical Berger code. The “weight-based” code has all the properties of the Berger code. Potentialities of the two codes for error detection in concurrent error detection circuits have been compared.

KEYWORDS

functional control, undetectable error, data bits, code Berger, weighted summation code, properties codes. 

REFERENCES

1. Goessel, M. and Graf, S. (1994), Error Detection Circuits,  McGraw-Hill, London, UK.
2. Pradhan, D.K. (1996), Fault-Tolerant Computer System Design, Prentice Hall.
3. Lala, P.K. (2001), Self-checking and Fault-tolerant Digital Design, University of Arkansas, USA.
4. Sapozhnikov, V.V. and  Sapozhnikov, Vl.V. (1992), Samoproveryaemye diskretnye ustroystva  [Self-checking, discrete devices],  Energoatomizdat, St. Petersburg, Russia.
5. Ryan, W.E. and  Shu, Lin (2009), Channel Codes. Classical and Modern,Cambridge University Press.
6. Berger, J.M. (1961), “А note on error detecting codes for asymmetric channels”, Information and Control, Vol. 4, no. 1, pp. 68-73.
7. Efanov, D.V., Sapozhnikov, V.V. and  Sapozhnikov, Vl.V. (2010), “The properties of the code-add in functional control circuits”, Avtomatika i telemekhanika, no. 6, pp. 155-162.
8. Sapozhnikov, V.V., Sapozhnikov, Vl.V. and  Efanov, D.V. (2010), “Limit properties of the code with the summation”, Izv. Peterburgskogo universiteta putey soobshcheniya, no.  3, pp. 290-299.
9. Blyudov, A.A., Sapozhnikov, V.V. and  Sapozhnikov, Vl.V. (2012), “A modified summation code for organizing control of combinatorial circuits”,  Avtomatika i telemekhanika, no.  1, pp. 169-177.
10. Blyudov, A., Efanov, D., Sapozhnikov, V. and  Sapozhnikov, Vl. (2012), “Properties of code with summation for logical circuit test organization”, Proc. of IEEE East-West Design&Test Symposium (EWDTS'2012),  Kharkov, Ukraine, September 14-17, 2012, pp. 114-117.
11. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V. and  Blyudov, A.A (2012), “On the question of the organization of self-checking circuits built using modular control codes summation”, Informatsionnye tekhnologii v upravlenii (ITU-2012). Materialy konferentsii  [Information Technologies in Management" (ITU 2012). Materials of the conference], St. Petersburg, GNTs RF OAO Kontsern TsNII «Elektropribor» pp. 656-661.
12. Blyudov, A.A., Efanov, D.V., Sapozhnikov, V.V. and  Sapozhnikov, Vl.V. (2012),  “Formation of the of Berger modified code  with the minimum number of data bits undetectable errors”,  Elektronnoe modelirovanie, Vol. 34, no.  6, pp. 17-29.
13. Gessel, M., Morozov, A.A., Sapozhnikov V.V. and  Sapozhnikov, Vl.V. (1997), “Study of combination of self-checking devices with independent monotone independent outputs”,  Avtomatika i telemekhanika, no.  2, pp. 180-193.
14. Sapozhnikov, V.V., Morozov, A., Sapozhnikov, Vl.V. and  Goessel, M. (1998), “A New Design Method for Self-Checking Unidirectional Combinational Circuits”,  J. of Electronic Testing: Theory and Applications,  Vol. 12, no.  2, pp. 41-53.
15. Das, D. and  Touba, N.A. (1999), “Weight-Based Codes and their Application to Concurrent Error Detection of Multilevel Circuits”,  Proc. 17th IEEE Test Symposium,  California, USA, pp. 370-376.
16. Favalli, M. and  Metra, C.(2001), “Optimization of error detecting codes for the detection of crosstalk originated errors”, Design, Automation and Test in Europe (DATE), March 13-16, 2001, pp. 290-296.

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DOLGIN V.P.

ABSTRACT

The method for solving the problem of determining intensities of the streams providing the preset properties of the queuing system is offered. The problem posing principles have been considered, simulation results have been presented.

KEYWORDS

service, the flow of events, the probability of states, the inverse problem. 

REFERENCES

1. Venttsel, E.S. and  Ovcharov, L.A.  (2000), Teoriya sluchaynykh protsessov i yeye inzhenernyye prilozheniya [Theory of random processes and its engineering applications], Vysshaya shkola,  Moscow, Russia.
2. Dyakonov, V.P. (1989), Spravochnik po algoritmam i programmam na yazyke beysik dlya personalnykh EVM [Handbook of algorithms and programs in the language BASIC for the personal computer], Nauka, Moscow, Russia.
3. Rotenberg, R.V. (1986), Osnovy nadezhnosti sistemy «voditel—avtomobil—doroga—sreda» [Fundamentals of reliability of the system "driver - vehicle - road - environment"], Mashinostroenie, Moscow, Russia. 

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GILGURT S.Ya.

ABSTRACT

A wide range of problems about a promising class of high performance digital devices—reconfigurable coprocessors based on FPGAs has been analyzed. A comparison with computation-intensive accelerators of another type was fulfilled. The obstacles that impede the propagation of reconfigurable coprocessors are investigated; the ways of their overcoming have been analyzed.

KEYWORDS

FPGA, reconfigurable  unified  coprocessor, coprocessor, accelerator. 

REFERENCES

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11. Melnyk, A.O., Melnyk, V.A. and  Sarayrekh, Z.T. (2010), “Use of  reconfigurable  accelerators to improve performance of personal computers”, Naukyy visnyk Chernivetskogo un-tu. Kompyuterni systemy ta komponenty, Vol. 1, no. 1, pp. 20-25.
12. Melnyk, V.A. and  Sarayrekh, Z. (2010), “Self-configurable  hardware accelerators for computers’  computations”,  Visnyk Nats. un-tu «Lvivska politekhnika». Kompyuterni systemy ta merezhi, no.  688, pp. 163-171.
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