Vector–Logic Synthesis of Deductive Matrices for Fault Simulation

W. Gharibi ¹, PhD, Prof., A. Hahanova ², Cand. T. Sc, Ass. Prof., V. Hahanov ²,
D. Sc., Prof., S. Chumachenko ², D. Sc., Prof., E. Litvinova ², D. Sc., Prof., I. Hahanov ²

¹ The University of Missouri-Kansas City MO 64110 USA,
  Ця електронна адреса захищена від спам-ботів. Вам необхідно увімкнути JavaScript, щоб побачити її.
² Kharkiv National University of Radio Electronics,
  Ukraine, 61166, Kharkiv, Nauka Avenue, 14,
  (057) 7021 326, Ця електронна адреса захищена від спам-ботів. Вам необхідно увімкнути JavaScript, щоб побачити її.

Èlektron. model. 2023, 45(2):16-33

https://doi.org/10.15407/emodel.45.02.016

АНОТАЦІЯ

The main idea is to create vector-logic computing that uses only read-write transactions on address memory to process large data. The main task is to implement new simple and reliable models and methods of vector computing based on primitive read-write transactions in the technology of vector flexible interpretive simulation of digital system faults. Vector-logic computing is a computational process based on read-write transactions over bits of a binary vector of functionality, where the input data is the addresses of the bits. A vector method for the synthesis of deductive matrices for transporting input fault lists is proposed, which has a quadratic computational complexity. The method is a development of the deductive vector synthesis algorithm based on the truth table. The deductive matrix is intended for the synthesis and verification of tests using parallel simulation of faults, as addresses, based on a read-write transaction of deductive vector cells in memory.

КЛЮЧОВІ СЛОВА:

vector computing, vector form of logic, matrix of deductive vectors, vector method for synthesizing a deductive matrix, read-write transaction, vector model of defects, functions and structures, deductive parallel fault simulation.

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